Software & Tools

Hardware Development

EDA and FPGA Flows

ARC works closely with a select number of industry leading EDA companies who develop tools and analytical techniques which ensure that the design intent of each uniquely configured ARC® Multimedia Subsystem or core is reflected in the final design that is transferred to silicon.

ARC and its closest EDA partners have developed reference methodologies which allow a seamless integration of the partner's front end tools and ARC’s patented ARChitect Processor Configurator Tool. The ARC and Cadence joint efforts are an example of this collaboration to develop specialized design reference methodologies optimized for low power portable multimedia applications. These efforts have been implemented as part of the Energy PRO Low Power Flow.

ARC partner EDA companies include:

Azuro Cadence Design Systems Chip Estimate Magma Design Automation Synopsys, Inc.

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Energy PRO Low Power Flow for Longest Battery Life

Implementing a system-level SoC power management strategy requires integration with industry-standard EDA flows. Like all of ARC's key technologies, Energy PRO is supported by first-class design and verification tools, allowing its integration into any industry-standard RTL-to-GDSII flow.

The ARChitect® IP Configurator captures the low-power design intent at the time the ARC® core is configured, and conveys that intent through the flow to tape-out, using industry standards such as UPF or CPF, or the designer's own preferred data interchange format.

In addition, we have worked with Cadence Design Systems and Virage Logic to produce a complete, validated reference design methodology (RDM) that offers designers a simple, highly integrated and automated development process. The RDM provides accurate simulation of power-down modes, automated insertion of isolation cells and level shifters during synthesis, and place-and-route tools that can accommodate the use of "voltage islands".

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